The present invention relates to a memory board system including a plurality of memory modules and a memory controller for controlling these memory modules to exchange data with the memory modules. The present invention further relates to a high-speed data transfer synchronizing system and high-speed data transfer synchronizing method capable of reliably performing high-speed data transfer in synchronism with a clock signal even in different device environments constructed of a memory controller and memory modules.
In the field of information processors, the performance of microprocessor units (MPUS) has improved, and the capacity of IC memories used has also greatly increased to 256 Mbits, 1 Gbits, and the like. Under the circumstances, it is becoming more and more important to efficiently transfer large amounts of data between a memory module including a plurality of IC memories and an MPU.
Generally, a memory board system is constructed by combining a plurality of memory modules and a memory controller.
FIG. 1 shows an outline of the arrangement of a memory board system. A clock generator CG formed in a memory controller (to be simply referred to as a controller hereinafter) MEC generates a clock signal. The clock signal generated by this clock generator CG is sequentially transferred as a clock signal TCLk along an array of a plurality of memory modules MM1 to MMn. This clock signal TCLK is returned in the position of the memory module MMn farthest from the controller MEC. The clock signal TCLK is then sequentially transferred as a clock signal RCLK in the opposite direction along the array of the memory modules and transmitted to the controller MEC. Note that each memory module is formed by, e.g., mounting a plurality of memory ICs on a print circuit board.
An output command from the controller MEC is transferred to the memory modules MM1 to MMn via a command bus. Each memory module receives the command from the command bus in synchronism with the clock signal TCLK and outputs data to a data bus line in synchronism with the clock signal RCLK. The readout data output from each memory module to the data bus line is input to the controller MEC.
Data to be written in each memory module is output from the controller to the data bus line. Each memory module receives the data from the data bus line in synchronism with the clock signal TCLK and writes the data in it. In addition to a clock bus line for transferring the clock signals TCLK and RCLK, the command bus line for transferring commands, and the data bus line for transferring data, this memory board system has an address bus line for transferring address signals. This address bus line is not shown in FIG. 1.
Each memory module generates two different internal clock signals synchronizing with the clock signals TCLK and RCLK and controls data read and write in synchronism with these two internal clock signals. A circuit for generating such internal clock signals is proposed as a Synchronous Adjustable Delay (SAD) in U.S. Ser. No. 08/839037 filed by the present inventor.
In the system shown in FIG. 1, the condition under which data transfer is normally performed is that the clock signals TCLK and RCLK transferred through the clock bus line and data transferred through the data bus line synchronize with each other at any instant. However, this condition is difficult to completely meet. This is so because it is difficult to completely equalize the physical conditions, e.g., the resistances and capacitances of the clock bus line for transferring the clock signals, the data bus line for transferring data, and the command bus line for transferring commands.
For this reason, even when one of the memory modules outputs data to the data bus line in synchronism with the clock signal RCLK, the clock signal RCLK and the data arrive at the controller with a slight time difference. This time difference naturally changes in accordance with the position of a memory module which outputs data. If a cycle time of the clock signal is much longer than this time difference, the controller can have a sufficiently long data window, i.e., data input period. So, this time difference is not a problem.
If the cycle time of the clock signal shortens, however, the time difference between the clock signal RCLK and data arriving at the controller is a problem. If this is the case, therefore, the physical conditions, e.g., the resistances of the clock bus line and the data bus line must be made as equal as possible to thereby decrease the time difference and perform high-speed data transfer.
Unfortunately, the degree of freedom of the memory system is lost when the above method is used. This will be described below with reference to FIGS. 2A and 2B.
FIG. 2A shows the arrangement of a memory board system including one controller MEC and three memory modules MM1 to MM3. FIG. 2B shows the arrangement of a memory board system including one controller MEC and four memory modules MM1 to MM4. The load conditions of the memory modules with respect to a clock bus line and data bus line are not necessarily the same. Accordingly, if the physical conditions of the clock bus line and data bus line are matched in one of the two systems, the conditions in the other system may differ from the matched conditions.
For example, assume that a signal propagates from the memory module MM3 to the controller MEC while the bus conditions are matched in the system shown in FIG. 2B. FIG. 3A shows the relationship between the timings of the clock signal RCLK and data at the position of the memory module MM3. in the systems shown in FIGS. 2A and 2B. FIG. 3B shows the relationship between the timings of the clock signal RCLK and data at the position of the controller MEC in the systems shown in FIGS. 2A and 2B.
The bus conditions are matched in the system shown in FIG. 2B. Therefore, in the system shown in FIG. 2B, the clock signal RCLK and data synchronize with each other at the position of the memory module MM3, as shown in FIG. 3A. In contrast, in the system shown in FIG. 2A, a bus delay time with respect to the clock signal RCLK is different. Accordingly, as shown in FIG. 3B, the clock signal RCLK and data do not synchronize with each other at the position of the controller MEC. For example, if the position of data moves as indicated by the thick lines in FIG. 3B, the controller can no longer receive the data at the timing of the leading edge of the clock,.signal RCLK.
Next, the influence of the characteristics of a bus line on a signal delay time will be described below. In an ideal case, if a signal line has a capacitance C and an inductance L per unit length (cm), a signal propagates the unit length for a time of (Cxc2x7L)xc2xd. In a general memory board system, if C is 5 to 7 pF and L is 15 to 20 nH, a signal delay time per unit length is 0.27 to 0.37 nS. Therefore, a variation in the signal delay time per unit length is (0.37xe2x88x920.27) nS=0.1 nS. If the length of the whole memory module is 10 cm, a variation in the signal delay time in the whole memory module is 1 nS. This means that even if timings in bus lines are optimized in a specific system constructed of a controller and some memory modules, a signal delay time is shifted about 1 nS in another system having a different number of memory modules.
If a data window, i.e., a data input period equivalent to this time variation is required, a clock signal cycle of 2 ns, in other words, a clock signal frequency of 500 MHz is the limit by which data transfer can be normally performed without strictly equalizing the physical conditions of bus lines. Note that a command is input in, e.g., every other cycle, rather than each cycle, with respect to the clock signal TCLK. That is, the timing of a command can be loosely defined compared to that of data. So, the same synchronism with the clock signal as that of data is unnecessary.
As described above, in the conventional memory board system including a plurality of memory modules and one memory controller, if the cycle of a clock signal shortens in order to increase the data transfer rate, no normal operation can be performed any longer depending on the position of a memory module along a bus line or on the environment of a bus system.
It is, therefore, an object of the present invention to provide a high-speed data transfer synchronizing system and high-speed data transfer synchronizing method capable of high-speed synchronous data transfer without very strictly limiting the physical conditions of bus lines between memory modules and a memory controller.
According to the present invention, there is provided a high-speed data transfer synchronizing system comprising a plurality of memory modules for receiving a clock signal to operate in synchronism with the clock signal, each of the memory modules having at least one internal clock signal generating circuit to generate at least one internal clock signal synchronizing with the clock signal from the clock signal and having a function of adjusting a generation timing of the internal clock signal and a memory controller for generating and supplying the clock signal to the memory modules and transferring/receiving data to/from the memory modules.
According to the present invention, there is provided a clock signal generating circuit comprising a first buffer circuit for receiving an external clock signal, a first delay circuit having a signal delay time substantially equal to a signal delay time in the first buffer circuit, the first delay circuit receiving an output signal from the first buffer circuit and delaying the output signal from the first buffer circuit, a second delay circuit for receiving an output signal from the first delay circuit and delaying the output signal from the first delay circuit by a predetermined time, a second buffer circuit for receiving an output signal from the second delay circuit, a third delay circuit comprising a plurality of cascaded multi-stage first delay units to receive an output signal from the second buffer circuit and delay the output signal from the second buffer circuit, by transmitting the signal by the plurality of first delay units, for a period corresponding to a cycle of the clock signal, a fourth delay circuit comprising a plurality of cascaded multi-stage second delay units to receive the signal delayed by the third delay circuit and delay the delayed signal by transmitting the signal by the same number of second delay units as the number of first delay units by which. the output signal from the second buffer circuit is transmitted, a variable delay circuit for receiving an output signal from the fourth delay circuit and outputting the output signal from the fourth delay circuit after delaying the signal by a time corresponding to a control signal, and a third buffer circuit having a signal delay time substantially equal to a signal delay time in the second buffer circuit, the third buffer circuit receiving an output signal from the variable delay circuit and generating an internal clock signal.
According to the present invention, there is provided a high-speed data transfer synchronizing method for a high-speed data transfer synchronizing system comprising a plurality of memory modules for receiving a clock signal to operate in synchronism with the clock signal, each of the memory modules having an internal clock signal generating circuit to generate at least one internal clock signal synchronizing with the clock signal from the clock signal and having a function of adjusting a generation timing of the internal clock signal and a memory controller for generating and supplying the clock signal to the memory modules and transferring/receiving data to/from the memory modules, and comprising the steps of storing a predetermined data pattern in the memory modules, reading out the data pattern stored in each memory module from the memory modules and transferring the readout data pattern to the memory controller, and comparing the data pattern transferred from each memory module with the original predetermined data pattern and generating the control signal such that the two data patterns match.
According to the present invention, there is provided a high-speed data transfer synchronizing method for a high-speed data transfer synchronizing system comprising a plurality of memory modules for receiving a clock signal to operate in synchronism with the clock signal, each of the memory modules having an internal clock signal generating circuit to generate at least one internal clock signal synchronizing with the clock signal from the clock signal and having a function of adjusting a generation timing of the internal clock signal and the memory modules previously storing a predetermined data pattern, a memory controller for generating and supplying the clock signal to the memory modules and transferring/receiving data to/from the memory modules, and, comprising the steps of reading out the data pattern previously stored in each memory module and transferring the readout data pattern to the memory controller, and comparing the data pattern transferred from each memory module with the original data pattern previously stored in each memory module and generating the control signal such that the two data patterns match.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.